NVIDIA’s Marco Framework Revolutionizes Chip Design with Multi-AI Agents

In a significant stride towards advancing chip design, NVIDIA has introduced the Marco framework, a cutting-edge approach that leverages configurable graph-based task solving and multi-AI agent configurations. This innovative framework aims to tackle the inherent complexities and lengthy turn-around times (TAT) associated with modern chip and hardware design, according to NVIDIA.

The Marco Framework

The Marco framework introduces a flexible system where tasks are broken down into sub-tasks represented as nodes within a graph. Each edge in the graph signifies the execution or knowledge relationship between these nodes, allowing for dynamic and static task configurations. This system supports both single and multiple AI agents configured in real-time, integrating chip-design knowledge such as circuits and timing.

Notably, the framework employs tools like VerilogCoder and RTLFixer, which utilize dynamic task graphs for specification-to-RTL processes and syntax error fixing, respectively. The framework also includes the MCMM timing analysis agent, which has demonstrated significant efficiency improvements in debugging and analyzing timing reports.

Advancing HDL Code Generation

One of the key applications of the Marco framework is in the generation of hardware description languages (HDLs) like Verilog. Given the increasing complexity of VLSI design, generating syntactically and functionally correct HDL code is a challenging task. The framework’s RTLFixer uses retrieval-augmented generation (RAG) and ReAct prompting to iteratively debug and correct syntax errors, while VerilogCoder employs a task and circuit relation graph (TCRG) to enhance code generation and debugging processes.

Innovative DRC Code Generation

The DRC-Coder agent within the Marco framework is another highlight, using multiple autonomous agents with vision capabilities to generate design rule check (DRC) codes. This agent interprets design rules from various formats, achieving perfect F1 scores in generating DRC codes for advanced technology nodes, significantly reducing the time required for code generation.

Optimization and Analysis

The Marco framework also enhances standard cell layout optimization through its LLM agents, which use natural language processing to optimize layout PPA and debug routability issues. Additionally, the MCMM timing analysis agent employs dynamic task graphs for efficient timing report analysis, achieving notable speedups compared to traditional methods.

Conclusion and Future Directions

NVIDIA’s Marco framework represents a transformative approach to chip design, utilizing collaborative LLM-based agents to enhance efficiency and performance. Future research directions include training LLMs with high-quality design data, improving debugging capabilities, and integrating PPA metrics into design workflows.

For further insights into NVIDIA’s electronic design automation initiatives, interested readers can explore the NVIDIA Design Automation Research Group’s publications and projects.

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